The SR latch: a circuit that remembers
Every circuit so far has had no memory: the outputs depended only on the inputs at that moment. The SR latch is different. It remembers one bit. Pulse S (set) and the output Q becomes 1. Pulse R (reset) and it becomes 0. With both inputs at 0, Q keeps whatever it was.
Step by step
The order matters here: the checker sets the inputs one row at a time, top to bottom, and the outputs must match each row.
| Step | S | R | Q |
|---|---|---|---|
| 1 | 1 | 0 | 1 |
| 2 | 0 | 0 | 1 |
| 3 | 0 | 1 | 0 |
| 4 | 0 | 0 | 0 |
| 5 | 1 | 0 | 1 |
| 6 | 0 | 0 | 1 |
How it works
Memory needs a loop: the output must feed back into the circuit. Take two NOR gates and connect the output of each one to an input of the other. Once Q is 1, the loop keeps it at 1 by itself, even after S goes back to 0. The same happens for 0 after a reset.
Because the order of events matters, the table below is a sequence, not a truth table: the checker sets the inputs row by row and Q must follow. Note the rows where S and R are both 0: the same inputs give different outputs, depending on what happened before. That is memory.
Setting S and R to 1 at the same time is not allowed in an SR latch: the output would be unpredictable when they are released.
Hints and solution
Try on your own first. Each hint gives away a little more.
- Memory needs a loop: feed outputs back into inputs.
- Two NOR gates, each taking the other’s output as one input.
- Q = NOR(R, Q̅) and Q̅ = NOR(S, Q).