The D flip-flop: memory that follows a clock
A D flip-flop stores one bit, but only at a precise moment: when the clock signal CLK goes from 0 to 1 (the rising edge). At that instant Q copies D. The rest of the time Q holds its value, whatever D does.
Step by step
The order matters here: the checker sets the inputs one row at a time, top to bottom, and the outputs must match each row.
| Step | D | CLK | Q |
|---|---|---|---|
| 1 | 0 | 0 | – |
| 2 | 0 | 1 | 0 |
| 3 | 1 | 1 | 0 |
| 4 | 1 | 0 | 0 |
| 5 | 1 | 1 | 1 |
| 6 | 0 | 1 | 1 |
| 7 | 0 | 0 | 1 |
| 8 | 0 | 1 | 0 |
Latch or flip-flop?
A D latch is simpler: while its enable input is 1 it lets D straight through to Q, and when enable goes to 0 it holds. The problem is that while enable is 1, every change of D reaches Q. A flip-flop reacts to one instant only, which is what makes a whole processor change state in step, once per clock tick.
How it works
Put two latches in a row: a master and a slave. The master is open while CLK is 0 and follows D. The slave is open while CLK is 1 and shows what the master holds. When the clock rises, the master closes on the last value of D and the slave passes exactly that value to Q. At no moment are both open, so D can never run straight through.
The table below is a sequence: the checker changes D and CLK row by row. An “x” means the value doesn’t matter yet, because nothing has been stored.
Hints and solution
Try on your own first. Each hint gives away a little more.
- A D latch copies D while its enable is 1. That is not enough: Q would change whenever D does while CLK is 1.
- Use two latches in a row (master and slave).
- The master is enabled while CLK is 0, the slave while CLK is 1.